Newly manufactured integrated circuits must be tested before they are shipped to customers. Integrated circuit manufacturing is just short of miraculous but defective parts can be produced. Integrated circuit manufacturers generally test every integrated circuit for compliance with the design guidelines. Most integrated circuit designs include scan data paths such as JTAG to input and output data on other than the circuits normal I/O ports. A typical technique includes entering a test pattern into the scan chain that places the integrated circuit in a known state. The device under test is then run normally for one or more machine cycles. The resulting data on the registers in the scan chain is read out and compared with expected results. Key factors in the cost of this testing is the amount of data to be transferred, tester time used and the extent of the operations covered by the test patterns used.
The amount of pattern data to be input and output is very large. Generally integrated circuits are manufactured with plural scan chains that can be loaded and read in parallel. Even with parallel scan chains the amount of data transferred is still large. One response to this data requirement is data compression. The tester sends compressed data to the device under test. The integrated circuit under test includes a decompressor to recover the original data for loading to a scan chain and a compressor for compressing the state data read out of the scan chain.
Multi-site testing using low test pin count and high compression techniques are commonly used techniques to reduce test time and test cost. High compression of test data can result in coverage loss due to the higher correlation in the test data loaded into scan flip-flops. A conventional response to such coverage loss includes using a no-compression mode or bypass mode automatic test pattern generation (ATPG). This uncompressed test pattern data covers the coverage loss of the highly compressed test pattern data. Empirical data shows this technique incurs a significant test time hit, defeating the objective of low test time.
The increasing push for reduced chip costs and test costs, make multi-site testing the de-facto test strategy. As the number of devices that can be tested in parallel increases, the number of tester I/O channels available for a single device decreases. These trends reduce the quality of manufacturing test for a single device. Reducing the number of scan channels requires an increase in the efficiency of compression which reduces coverage due to higher correlation between test data. This higher correlation restricts the type of patterns that can be generated and lowers coverage about 2 to 3% to an unacceptable level.